The present invention relates to analog-to-digital converters and more specifically to an improved comparator circuit for use in analog-to-digital converters.
The comparator circuit of an analog-to-digital converter includes an input signal compared against a reference signal and subsequently digitized. One form of analog-to-digital conversion includes a flash quantization. As illustrated in FIG. 1, a parallel string of comparators is used to compare the analog input voltage directly to voltage steps on a resistive ladder. The results of the comparison are provided to a latch which indicates whether the output of the comparator is high or low. These results are then decoded by a tap detection logic or decoder and provided as digital output signals. A typical single latch configuration of the prior art is illustrated in FIG. 1.
A flash converter is rapid because the signal is propagated in parallel connected comparators and decoding logic. As a tradeoff, the flash converter is more complex requiring a greater number of comparators, a decoding logic dependent upon the number of bits and an input resistor string.
As discussed in U.S. Pat. No. 4,691,189 to Dingwall, et al, single latch circuits may provide erroneous results. The Dingwall, et al patent suggests using a D type master-slave flip-flop (DMSFF) following a two stage autozero comparator. The use of DMSFF gives poor resolution since the threshold of the first D latch stage varies with the processing temperature and supply voltage. The same clock that is used in the autozero comparator is used in the DMSFF latches.
Thus it is an object of the present invention to provide a flash converter with improved accuracy and resolution.
Another object of the present invention is to provide a flash converter whose resolution is independent of processing and temperature induced changes.
These and other objects are achieved by providing a comparator circuit wherein the circuit includes a comparator for comparing the input signal to the reference signal, a sense amplifier connected to the output of the comparator for sensing and providing an amplified signal and an output circuitry connecting the output of the sensed amplifier for receiving and latching the amplified signal. The comparator would include a two-stage autozero comparator. The sense amplifier includes a differential amplifier having a first input connected to the output of the comparator and a second input connected to a second reference signal. A reference signal generator would produce the second reference signal. The output stage of the reference signal generator would match the output stage of the comparator. Thus the sense amplifier will not be affected by processing or temperature variations since the reference signal generated will track the output of the comparator stage. The sense amplifier would include input and output buffer circuits. The sense amplifier minimizes loading on the autozero comparator stage and achieves the speed of a D-type latch while providing greater accuracy and resolution since true differential amplification is taking place.
The output stage of the comparator would include a decoder having its input connected to the output of the sense amplifier and a latch connected to the output of the decoder. By providing the decoding after the sense amplifier and before the latch circuitry, the delay of the latch circuitry occurs after the decoding. The latch circuitry preferably is a DMSFF so as to provide a valid output for the entire clock period instead of the validity for only half the clock period as would be true if using a single D-latch. A clock signal is used to control the comparator circuits while a strobe signal is used to control the sense amplifier and latches. This provides independent control of the input sampling and holding as well as the subsequent signal processing. The strobe signal leads the clock signal with respect to phase.
When a plurality of the comparator circuits is used in a flash analog-to-digital converter, a common second reference signal generator may be used for one or more of the comparators. Thus for example, each row column may include its own reference signal generator.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.